| Rosetta Standards Committee Presentation |
Presentation will be available when the show starts on
June 24, 2003.
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Dr. Perry Alexander
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Abstract:
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Dr. Alexander's 10 minute narrated presentation explains in detail the status and future directions of the Rosetta Standardization Process.
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Bio:
Dr.Perry Alexander is currently an Associate Professor in the Electrical Engineering and Computer Science Department and member of the Information and Telecommunication Technology Center at The University of Kansas. His research interests include systems level modeling, active network modeling, component retrieval and reuse, architecture and heterogeneous analysis. More ...
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| SystemVerilog Assertions - Language Tutorial |
Presentation will be available when the show starts on
June 24, 2003.
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Dr. Bassam Tabbara, Technical Manager, R&D, Novas Software, Inc.
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Abstract:
| Dr. Bassam's 35 minute narrated presentation explains in detail what assertions are, and how to work with them in SystemVerilog. |
Bio:
Dr.Bassam Tabbara is the Technical manager for R&D at Novas. Bassam received his doctoral degree from Berkeley in 2000. More ...
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| SystemVerilog - PSL LRM Overview |
Presentation will be available when the show starts on
June 24, 2003.
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Harry D. Foster, Chair FVTC, Chief Methodologist, Jasper Design Automation
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Abstract:
| PSL 1.01 has been completed, is well-defined and semantically sound and is available. PSL 1.1 is starting and will provide the semantic framework for SVA definition with alignment of PSL and SVA the goal. |
Bio:
Harry Foster serves as Chairman of the Accellera Formal Verification Technical Committee, which is currently defining the PSL property specification language standard.He is co-author of the new Kluwer Academic Publishers book Assertion-Based Design, as well as the Kluwer book Principles of Verifiable RTL Design.Harry is Jasper Design Automation Chief Methodologis. More ...
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| SystemVerilog 3.1 - Design Subset |
Presentation will be available when the show starts on
June 24, 2003.
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Johny Srouji, Intel, Chair -SV-Basic Committee
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Abstract:
| SV 3.1 is a very rich RTL language and this presentation will provide a flavor of some of the enhancements in SV3.1, wrt Data Types, Structs & Unions, Literal, Enums, Constants & Parameters and Variables Scope & Lifetime. |
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Bio:
Johny Srouji is the group lead for High Level & RTL Tools and Technologies at Intel CAD Department in Haifa.Johny has been with Intel for a total of 10 years, and has held a variety of technical and management positions in TDC (Texas Design Center in Austin) and IDC (Israel Design Center in Haifa).In TDC, Johny was the manager of Front End tools and design methodologies in the areas of design, simulation, dynamic validation, Boolean equivalence verification, and Formal verification and DFT tools. More ...
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| User Experience with SystemVerilog for Design |
Presentation will be available when the show starts on
June 24, 2003.
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Matt Maidment, Sr. CAD Engineer, Intel Corporation
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Abstract:
| Matt's narrated presentation centers on the user experience. It covers the guiding principles, data organization, capturing more design intent, and more. |
Bio:
Matt Maidment currently works on the Intel DPG RTL Design Methodology Team
located in Hillsboro, Oregon. During his 6 years at Intel, Matt has worked on RTL
Design and Verification tools and methodologies for several microprocessor
projects. Matt received his Bachelor's and Master's degrees in Electrical Engineering
from Ohio State University.
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| Integrating Assertion and Testbench DV Methodologies |
Presentation will be available when the show starts on
June 24, 2003.
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Jon Michelson, Principal and Author, Verification Central
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Abstract:
| This narrated presentation covers the typical functional DV testbench, briefly discusses assertions, and shows you step-by-step integration of assertions and testbench methodologies. |
Bio:
Jon Michelson is Principal and author at Verification Central. He has extensive experience verifying complex designs and writing verification infrastructure tools, and is the co-author of 'The Art of Verification with Vera.' He is currently designing and verifying complex networking systems.
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| Tutorial of Verification Features in System Verilog |
Presentation will be available when the show starts on
June 24, 2003.
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Tom Fitzpatrick
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Abstract:
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This narrated presentation provides a tutorial of the verification features in System Verilog.
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Bio:
Tom Fitzpatrick has over 16 years experience in the hardware and EDA industries, bringing an extensive background as a design and verification engineer to bear on product requirements and methodology definition for various simulation, debug and formal verification tools. He has been an active member of the IEEE 1364-2001 Verilog and Accellera SystemVerilog standards committees, as well as being part of the Superlog language design team at Co-Design Automation, prior to their recent acquisition by Synopsys. At Synopsys, Tom is currently responsible for driving language strategy and defining verification tools and methodologies around SystemVerilog.
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| Design Debugging Using Xilinx? Virtex? Register State Capture Technology |
Presentation will be available when the show starts on
June 24, 2003.
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Raj K. Mathur
Director, Software Product Management, Aptix Corporation
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Abstract:
In PSPs, SoC or ASIC designs are mapped in multiple FPGAs and used to verify the functionality of the hardware, software and firmware design.This verification method operates at frequencies orders of magnitude above classical simulation.During hardware design debugging, visibility of all the internal registers of the design is necessary to isolate design bugs. More ...
Bio:
Raj Mathur is responsible for software product management including product direction at Aptix Corporation. His focus is software product development with productivity, as well as quality and technical innovations. He holds a Bachelor's degree in Electrical Engineering (1990) and worked as a design engineer at Analog Devices and Stanford Research Systems, before joining Aptix Corporation in 1994.
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