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SystemVerilog Assertions - Language Tutorial Presentation will be available when the show starts on June 24, 2003.
SystemVerilog Assertions - Language Tutorial
Dr. Bassam Tabbara, Technical Manager, R&D, Novas Software, Inc.
Abstract:
Dr. Bassam's 35 minute narrated presentation explains in detail what assertions are, and how to work with them in SystemVerilog.


Bio:
Dr. Bassam Tabbara is the Technical manager for R&D at Novas. Bassam received his doctoral degree from Berkeley in 2000. His research interests include optimization, synthesis, and verification of hardware/software systems. He has authored numerous papers, and two books on these topics. He is currently leading the debug for assertion-based verification at Novas, and has been involved in Accellera SystemVerilog committees since 3.0 and now 3.1.



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